<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<meta name="generator" content="Doxygen 1.8.14"/>
<meta name="viewport" content="width=device-width, initial-scale=1"/>
<title>uartps: xuartps_hw.h File Reference</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="resize.js"></script>
<script type="text/javascript" src="navtreedata.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript">
  $(document).ready(initResizable);
</script>
<link href="doxygen.css" rel="stylesheet" type="text/css" />
<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
 <tbody>
 <tr style="height: 56px;">
  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
  <td id="projectalign" style="padding-left: 0.5em;">
   <div id="projectname">uartps
   </div>
   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
  </td>
 </tr>
 </tbody>
</table>
</div>
<!-- end header part -->
<!-- Generated by Doxygen 1.8.14 -->
<script type="text/javascript" src="menudata.js"></script>
<script type="text/javascript" src="menu.js"></script>
<script type="text/javascript">
$(function() {
  initMenu('',false,false,'search.php','Search');
});
</script>
<div id="main-nav"></div>
</div><!-- top -->
<div id="side-nav" class="ui-resizable side-nav-resizable">
  <div id="nav-tree">
    <div id="nav-tree-contents">
      <div id="nav-sync" class="sync"></div>
    </div>
  </div>
  <div id="splitbar" style="-moz-user-select:none;" 
       class="ui-resizable-handle">
  </div>
</div>
<script type="text/javascript">
$(document).ready(function(){initNavTree('xuartps__hw_8h.html','');});
</script>
<div id="doc-content">
<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a> &#124;
<a href="#func-members">Functions</a>  </div>
  <div class="headertitle">
<div class="title">xuartps_hw.h File Reference</div>  </div>
</div><!--header-->
<div class="contents">
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga16be7534dc3d678f8abcfeb87e6a4f7e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga16be7534dc3d678f8abcfeb87e6a4f7e">XUartPs_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:ga16be7534dc3d678f8abcfeb87e6a4f7e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read a UART register.  <a href="group__uartps__v3__1.html#ga16be7534dc3d678f8abcfeb87e6a4f7e">More...</a><br /></td></tr>
<tr class="separator:ga16be7534dc3d678f8abcfeb87e6a4f7e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab541297d822b163193a2e47305987ab6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gab541297d822b163193a2e47305987ab6">XUartPs_WriteReg</a>(BaseAddress,  RegOffset,  RegisterValue)&#160;&#160;&#160;Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))</td></tr>
<tr class="memdesc:gab541297d822b163193a2e47305987ab6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write a UART register.  <a href="group__uartps__v3__1.html#gab541297d822b163193a2e47305987ab6">More...</a><br /></td></tr>
<tr class="separator:gab541297d822b163193a2e47305987ab6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac8b8f06d10cf178227ce88c140d78eb4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gac8b8f06d10cf178227ce88c140d78eb4">XUartPs_IsReceiveData</a>(BaseAddress)</td></tr>
<tr class="memdesc:gac8b8f06d10cf178227ce88c140d78eb4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if there is receive data in the receiver and/or FIFO.  <a href="group__uartps__v3__1.html#gac8b8f06d10cf178227ce88c140d78eb4">More...</a><br /></td></tr>
<tr class="separator:gac8b8f06d10cf178227ce88c140d78eb4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1507e8d7b12983484a0ab5436a51970"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gaf1507e8d7b12983484a0ab5436a51970">XUartPs_IsTransmitFull</a>(BaseAddress)</td></tr>
<tr class="memdesc:gaf1507e8d7b12983484a0ab5436a51970"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if a byte of data can be sent with the transmitter.  <a href="group__uartps__v3__1.html#gaf1507e8d7b12983484a0ab5436a51970">More...</a><br /></td></tr>
<tr class="separator:gaf1507e8d7b12983484a0ab5436a51970"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for the UART. </p>
</div></td></tr>
<tr class="memitem:ga90a3cb2c33dba6a5b888f7324d1c5135"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga90a3cb2c33dba6a5b888f7324d1c5135">XUARTPS_CR_OFFSET</a>&#160;&#160;&#160;0x0000U</td></tr>
<tr class="memdesc:ga90a3cb2c33dba6a5b888f7324d1c5135"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register [8:0].  <a href="group__uartps__v3__1.html#ga90a3cb2c33dba6a5b888f7324d1c5135">More...</a><br /></td></tr>
<tr class="separator:ga90a3cb2c33dba6a5b888f7324d1c5135"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad4932468a404b116c0e56b496b906716"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gad4932468a404b116c0e56b496b906716">XUARTPS_MR_OFFSET</a>&#160;&#160;&#160;0x0004U</td></tr>
<tr class="memdesc:gad4932468a404b116c0e56b496b906716"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode Register [9:0].  <a href="group__uartps__v3__1.html#gad4932468a404b116c0e56b496b906716">More...</a><br /></td></tr>
<tr class="separator:gad4932468a404b116c0e56b496b906716"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga50985f0d8e60110fbbc63b1e100beb68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga50985f0d8e60110fbbc63b1e100beb68">XUARTPS_IER_OFFSET</a>&#160;&#160;&#160;0x0008U</td></tr>
<tr class="memdesc:ga50985f0d8e60110fbbc63b1e100beb68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable [12:0].  <a href="group__uartps__v3__1.html#ga50985f0d8e60110fbbc63b1e100beb68">More...</a><br /></td></tr>
<tr class="separator:ga50985f0d8e60110fbbc63b1e100beb68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e39d2ae49038a4ce4087bbee2bfdab7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga7e39d2ae49038a4ce4087bbee2bfdab7">XUARTPS_IDR_OFFSET</a>&#160;&#160;&#160;0x000CU</td></tr>
<tr class="memdesc:ga7e39d2ae49038a4ce4087bbee2bfdab7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Disable [12:0].  <a href="group__uartps__v3__1.html#ga7e39d2ae49038a4ce4087bbee2bfdab7">More...</a><br /></td></tr>
<tr class="separator:ga7e39d2ae49038a4ce4087bbee2bfdab7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0cfdb73d2795d7cc3b849fe1622fa029"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga0cfdb73d2795d7cc3b849fe1622fa029">XUARTPS_IMR_OFFSET</a>&#160;&#160;&#160;0x0010U</td></tr>
<tr class="memdesc:ga0cfdb73d2795d7cc3b849fe1622fa029"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Mask [12:0].  <a href="group__uartps__v3__1.html#ga0cfdb73d2795d7cc3b849fe1622fa029">More...</a><br /></td></tr>
<tr class="separator:ga0cfdb73d2795d7cc3b849fe1622fa029"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e96d23606d96a7d9816bc2ff777cbf8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga7e96d23606d96a7d9816bc2ff777cbf8">XUARTPS_ISR_OFFSET</a>&#160;&#160;&#160;0x0014U</td></tr>
<tr class="memdesc:ga7e96d23606d96a7d9816bc2ff777cbf8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status [12:0].  <a href="group__uartps__v3__1.html#ga7e96d23606d96a7d9816bc2ff777cbf8">More...</a><br /></td></tr>
<tr class="separator:ga7e96d23606d96a7d9816bc2ff777cbf8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga77bb5a0dfa2f1e62cf75c0972e889e92"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga77bb5a0dfa2f1e62cf75c0972e889e92">XUARTPS_BAUDGEN_OFFSET</a>&#160;&#160;&#160;0x0018U</td></tr>
<tr class="memdesc:ga77bb5a0dfa2f1e62cf75c0972e889e92"><td class="mdescLeft">&#160;</td><td class="mdescRight">Baud Rate Generator [15:0].  <a href="group__uartps__v3__1.html#ga77bb5a0dfa2f1e62cf75c0972e889e92">More...</a><br /></td></tr>
<tr class="separator:ga77bb5a0dfa2f1e62cf75c0972e889e92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3370f0abee2b4247e3c4aecda1fd63e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga3370f0abee2b4247e3c4aecda1fd63e7">XUARTPS_RXTOUT_OFFSET</a>&#160;&#160;&#160;0x001CU</td></tr>
<tr class="memdesc:ga3370f0abee2b4247e3c4aecda1fd63e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX Timeout [7:0].  <a href="group__uartps__v3__1.html#ga3370f0abee2b4247e3c4aecda1fd63e7">More...</a><br /></td></tr>
<tr class="separator:ga3370f0abee2b4247e3c4aecda1fd63e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc29194aeedab160158a6d44c647224e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gabc29194aeedab160158a6d44c647224e">XUARTPS_RXWM_OFFSET</a>&#160;&#160;&#160;0x0020U</td></tr>
<tr class="memdesc:gabc29194aeedab160158a6d44c647224e"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX FIFO Trigger Level [5:0].  <a href="group__uartps__v3__1.html#gabc29194aeedab160158a6d44c647224e">More...</a><br /></td></tr>
<tr class="separator:gabc29194aeedab160158a6d44c647224e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2a501f754853b4aa5aaa151a2b8f8bb7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga2a501f754853b4aa5aaa151a2b8f8bb7">XUARTPS_MODEMCR_OFFSET</a>&#160;&#160;&#160;0x0024U</td></tr>
<tr class="memdesc:ga2a501f754853b4aa5aaa151a2b8f8bb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Modem Control [5:0].  <a href="group__uartps__v3__1.html#ga2a501f754853b4aa5aaa151a2b8f8bb7">More...</a><br /></td></tr>
<tr class="separator:ga2a501f754853b4aa5aaa151a2b8f8bb7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga36a307fcdb77eba28c8029f92d4db1b9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga36a307fcdb77eba28c8029f92d4db1b9">XUARTPS_MODEMSR_OFFSET</a>&#160;&#160;&#160;0x0028U</td></tr>
<tr class="memdesc:ga36a307fcdb77eba28c8029f92d4db1b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Modem Status [8:0].  <a href="group__uartps__v3__1.html#ga36a307fcdb77eba28c8029f92d4db1b9">More...</a><br /></td></tr>
<tr class="separator:ga36a307fcdb77eba28c8029f92d4db1b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga342083b04c2f9d589d7dcb1d40b329f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga342083b04c2f9d589d7dcb1d40b329f6">XUARTPS_SR_OFFSET</a>&#160;&#160;&#160;0x002CU</td></tr>
<tr class="memdesc:ga342083b04c2f9d589d7dcb1d40b329f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel Status [14:0].  <a href="group__uartps__v3__1.html#ga342083b04c2f9d589d7dcb1d40b329f6">More...</a><br /></td></tr>
<tr class="separator:ga342083b04c2f9d589d7dcb1d40b329f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga12e256a5c0dd76b4c3ce5952382a0400"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga12e256a5c0dd76b4c3ce5952382a0400">XUARTPS_FIFO_OFFSET</a>&#160;&#160;&#160;0x0030U</td></tr>
<tr class="memdesc:ga12e256a5c0dd76b4c3ce5952382a0400"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO [7:0].  <a href="group__uartps__v3__1.html#ga12e256a5c0dd76b4c3ce5952382a0400">More...</a><br /></td></tr>
<tr class="separator:ga12e256a5c0dd76b4c3ce5952382a0400"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga18d29d65e26d6c7c192464dbf88aeb55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga18d29d65e26d6c7c192464dbf88aeb55">XUARTPS_BAUDDIV_OFFSET</a>&#160;&#160;&#160;0x0034U</td></tr>
<tr class="memdesc:ga18d29d65e26d6c7c192464dbf88aeb55"><td class="mdescLeft">&#160;</td><td class="mdescRight">Baud Rate Divider [7:0].  <a href="group__uartps__v3__1.html#ga18d29d65e26d6c7c192464dbf88aeb55">More...</a><br /></td></tr>
<tr class="separator:ga18d29d65e26d6c7c192464dbf88aeb55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d02d59e19b92baf8fa69dc24833f8a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga7d02d59e19b92baf8fa69dc24833f8a2">XUARTPS_FLOWDEL_OFFSET</a>&#160;&#160;&#160;0x0038U</td></tr>
<tr class="memdesc:ga7d02d59e19b92baf8fa69dc24833f8a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flow Delay [5:0].  <a href="group__uartps__v3__1.html#ga7d02d59e19b92baf8fa69dc24833f8a2">More...</a><br /></td></tr>
<tr class="separator:ga7d02d59e19b92baf8fa69dc24833f8a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3a498a8321302dae35403f698056058d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga3a498a8321302dae35403f698056058d">XUARTPS_TXWM_OFFSET</a>&#160;&#160;&#160;0x0044U</td></tr>
<tr class="memdesc:ga3a498a8321302dae35403f698056058d"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX FIFO Trigger Level [5:0].  <a href="group__uartps__v3__1.html#ga3a498a8321302dae35403f698056058d">More...</a><br /></td></tr>
<tr class="separator:ga3a498a8321302dae35403f698056058d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad9a37d71fe0f2e6912ad610faae42615"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gad9a37d71fe0f2e6912ad610faae42615">XUARTPS_RXBS_OFFSET</a>&#160;&#160;&#160;0x0048U</td></tr>
<tr class="memdesc:gad9a37d71fe0f2e6912ad610faae42615"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX FIFO Byte Status [11:0].  <a href="group__uartps__v3__1.html#gad9a37d71fe0f2e6912ad610faae42615">More...</a><br /></td></tr>
<tr class="separator:gad9a37d71fe0f2e6912ad610faae42615"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The Control register (CR) controls the major functions of the device.</p>
<p>Control Register Bit Definition </p>
</div></td></tr>
<tr class="memitem:ga997014ffed40da258769e496544cad9f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga997014ffed40da258769e496544cad9f">XUARTPS_CR_STOPBRK</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:ga997014ffed40da258769e496544cad9f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stop transmission of break.  <a href="group__uartps__v3__1.html#ga997014ffed40da258769e496544cad9f">More...</a><br /></td></tr>
<tr class="separator:ga997014ffed40da258769e496544cad9f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafb47359849b90befe1daa9b8b571cd41"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gafb47359849b90befe1daa9b8b571cd41">XUARTPS_CR_STARTBRK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:gafb47359849b90befe1daa9b8b571cd41"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set break.  <a href="group__uartps__v3__1.html#gafb47359849b90befe1daa9b8b571cd41">More...</a><br /></td></tr>
<tr class="separator:gafb47359849b90befe1daa9b8b571cd41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3fbd9a70a2d90299418dd9b5a16b94d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga3fbd9a70a2d90299418dd9b5a16b94d9">XUARTPS_CR_TORST</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga3fbd9a70a2d90299418dd9b5a16b94d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX timeout counter restart.  <a href="group__uartps__v3__1.html#ga3fbd9a70a2d90299418dd9b5a16b94d9">More...</a><br /></td></tr>
<tr class="separator:ga3fbd9a70a2d90299418dd9b5a16b94d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4831dbafe987c3286b022f3ab937bc9a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga4831dbafe987c3286b022f3ab937bc9a">XUARTPS_CR_TX_DIS</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga4831dbafe987c3286b022f3ab937bc9a"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX disabled.  <a href="group__uartps__v3__1.html#ga4831dbafe987c3286b022f3ab937bc9a">More...</a><br /></td></tr>
<tr class="separator:ga4831dbafe987c3286b022f3ab937bc9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf22f08ec08cbe06a53efbd44a43b8096"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gaf22f08ec08cbe06a53efbd44a43b8096">XUARTPS_CR_TX_EN</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gaf22f08ec08cbe06a53efbd44a43b8096"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX enabled.  <a href="group__uartps__v3__1.html#gaf22f08ec08cbe06a53efbd44a43b8096">More...</a><br /></td></tr>
<tr class="separator:gaf22f08ec08cbe06a53efbd44a43b8096"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaffa7bb80501ee66683ce853436190ea9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gaffa7bb80501ee66683ce853436190ea9">XUARTPS_CR_RX_DIS</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gaffa7bb80501ee66683ce853436190ea9"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX disabled.  <a href="group__uartps__v3__1.html#gaffa7bb80501ee66683ce853436190ea9">More...</a><br /></td></tr>
<tr class="separator:gaffa7bb80501ee66683ce853436190ea9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga31a05c9637d59b0631b43758a78d605e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga31a05c9637d59b0631b43758a78d605e">XUARTPS_CR_RX_EN</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga31a05c9637d59b0631b43758a78d605e"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX enabled.  <a href="group__uartps__v3__1.html#ga31a05c9637d59b0631b43758a78d605e">More...</a><br /></td></tr>
<tr class="separator:ga31a05c9637d59b0631b43758a78d605e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae297afa5ad30bb459ae92c6289bf24d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gae297afa5ad30bb459ae92c6289bf24d3">XUARTPS_CR_EN_DIS_MASK</a>&#160;&#160;&#160;0x0000003CU</td></tr>
<tr class="memdesc:gae297afa5ad30bb459ae92c6289bf24d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable/disable Mask.  <a href="group__uartps__v3__1.html#gae297afa5ad30bb459ae92c6289bf24d3">More...</a><br /></td></tr>
<tr class="separator:gae297afa5ad30bb459ae92c6289bf24d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1859f5cbbdbf0a83eff49960ccc342e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga1859f5cbbdbf0a83eff49960ccc342e2">XUARTPS_CR_TXRST</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga1859f5cbbdbf0a83eff49960ccc342e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX logic reset.  <a href="group__uartps__v3__1.html#ga1859f5cbbdbf0a83eff49960ccc342e2">More...</a><br /></td></tr>
<tr class="separator:ga1859f5cbbdbf0a83eff49960ccc342e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga659be76f18f938134bbe4e8c0e26159b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga659be76f18f938134bbe4e8c0e26159b">XUARTPS_CR_RXRST</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga659be76f18f938134bbe4e8c0e26159b"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX logic reset.  <a href="group__uartps__v3__1.html#ga659be76f18f938134bbe4e8c0e26159b">More...</a><br /></td></tr>
<tr class="separator:ga659be76f18f938134bbe4e8c0e26159b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Mode Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The mode register (MR) defines the mode of transfer as well as the data format.</p>
<p>If this register is modified during transmission or reception, data validity cannot be guaranteed.</p>
<p>Mode Register Bit Definition </p>
</div></td></tr>
<tr class="memitem:ga36d6b2e37f0201d8e6ecb20ab4835d83"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga36d6b2e37f0201d8e6ecb20ab4835d83">XUARTPS_MR_CCLK</a>&#160;&#160;&#160;0x00000400U</td></tr>
<tr class="memdesc:ga36d6b2e37f0201d8e6ecb20ab4835d83"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input clock selection.  <a href="group__uartps__v3__1.html#ga36d6b2e37f0201d8e6ecb20ab4835d83">More...</a><br /></td></tr>
<tr class="separator:ga36d6b2e37f0201d8e6ecb20ab4835d83"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadbf78ca00f2906f2b1334c1daa9e8688"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gadbf78ca00f2906f2b1334c1daa9e8688">XUARTPS_MR_CHMODE_R_LOOP</a>&#160;&#160;&#160;0x00000300U</td></tr>
<tr class="memdesc:gadbf78ca00f2906f2b1334c1daa9e8688"><td class="mdescLeft">&#160;</td><td class="mdescRight">Remote loopback mode.  <a href="group__uartps__v3__1.html#gadbf78ca00f2906f2b1334c1daa9e8688">More...</a><br /></td></tr>
<tr class="separator:gadbf78ca00f2906f2b1334c1daa9e8688"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a3141d2830527a27bf715a0b286936e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga0a3141d2830527a27bf715a0b286936e">XUARTPS_MR_CHMODE_L_LOOP</a>&#160;&#160;&#160;0x00000200U</td></tr>
<tr class="memdesc:ga0a3141d2830527a27bf715a0b286936e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Local loopback mode.  <a href="group__uartps__v3__1.html#ga0a3141d2830527a27bf715a0b286936e">More...</a><br /></td></tr>
<tr class="separator:ga0a3141d2830527a27bf715a0b286936e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga23f5cd17565cb514d2cb651a84b0bd71"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga23f5cd17565cb514d2cb651a84b0bd71">XUARTPS_MR_CHMODE_ECHO</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:ga23f5cd17565cb514d2cb651a84b0bd71"><td class="mdescLeft">&#160;</td><td class="mdescRight">Auto echo mode.  <a href="group__uartps__v3__1.html#ga23f5cd17565cb514d2cb651a84b0bd71">More...</a><br /></td></tr>
<tr class="separator:ga23f5cd17565cb514d2cb651a84b0bd71"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab9c582f58d3628334fa95502f7532c81"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gab9c582f58d3628334fa95502f7532c81">XUARTPS_MR_CHMODE_NORM</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:gab9c582f58d3628334fa95502f7532c81"><td class="mdescLeft">&#160;</td><td class="mdescRight">Normal mode.  <a href="group__uartps__v3__1.html#gab9c582f58d3628334fa95502f7532c81">More...</a><br /></td></tr>
<tr class="separator:gab9c582f58d3628334fa95502f7532c81"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5ed18906d4a19e7f047705902342e758"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga5ed18906d4a19e7f047705902342e758">XUARTPS_MR_CHMODE_SHIFT</a>&#160;&#160;&#160;8U</td></tr>
<tr class="memdesc:ga5ed18906d4a19e7f047705902342e758"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode shift.  <a href="group__uartps__v3__1.html#ga5ed18906d4a19e7f047705902342e758">More...</a><br /></td></tr>
<tr class="separator:ga5ed18906d4a19e7f047705902342e758"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3097ef040f183de6a8ba8b4cedf64ccf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga3097ef040f183de6a8ba8b4cedf64ccf">XUARTPS_MR_CHMODE_MASK</a>&#160;&#160;&#160;0x00000300U</td></tr>
<tr class="memdesc:ga3097ef040f183de6a8ba8b4cedf64ccf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode mask.  <a href="group__uartps__v3__1.html#ga3097ef040f183de6a8ba8b4cedf64ccf">More...</a><br /></td></tr>
<tr class="separator:ga3097ef040f183de6a8ba8b4cedf64ccf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac84dacebc9843a8f520379faa06ba5ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gac84dacebc9843a8f520379faa06ba5ac">XUARTPS_MR_STOPMODE_2_BIT</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:gac84dacebc9843a8f520379faa06ba5ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">2 stop bits  <a href="group__uartps__v3__1.html#gac84dacebc9843a8f520379faa06ba5ac">More...</a><br /></td></tr>
<tr class="separator:gac84dacebc9843a8f520379faa06ba5ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1f97e278219f4c7e2dd04f586713539d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga1f97e278219f4c7e2dd04f586713539d">XUARTPS_MR_STOPMODE_1_5_BIT</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga1f97e278219f4c7e2dd04f586713539d"><td class="mdescLeft">&#160;</td><td class="mdescRight">1.5 stop bits  <a href="group__uartps__v3__1.html#ga1f97e278219f4c7e2dd04f586713539d">More...</a><br /></td></tr>
<tr class="separator:ga1f97e278219f4c7e2dd04f586713539d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3b4e88eab034a961b86ab592369fb766"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga3b4e88eab034a961b86ab592369fb766">XUARTPS_MR_STOPMODE_1_BIT</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga3b4e88eab034a961b86ab592369fb766"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 stop bit  <a href="group__uartps__v3__1.html#ga3b4e88eab034a961b86ab592369fb766">More...</a><br /></td></tr>
<tr class="separator:ga3b4e88eab034a961b86ab592369fb766"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga26f962080857bd73db4cd09de29d1140"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga26f962080857bd73db4cd09de29d1140">XUARTPS_MR_STOPMODE_SHIFT</a>&#160;&#160;&#160;6U</td></tr>
<tr class="memdesc:ga26f962080857bd73db4cd09de29d1140"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stop bits shift.  <a href="group__uartps__v3__1.html#ga26f962080857bd73db4cd09de29d1140">More...</a><br /></td></tr>
<tr class="separator:ga26f962080857bd73db4cd09de29d1140"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc83d5b2b747a1d1eac63c5067cf0e88"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gadc83d5b2b747a1d1eac63c5067cf0e88">XUARTPS_MR_STOPMODE_MASK</a>&#160;&#160;&#160;0x000000A0U</td></tr>
<tr class="memdesc:gadc83d5b2b747a1d1eac63c5067cf0e88"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stop bits mask.  <a href="group__uartps__v3__1.html#gadc83d5b2b747a1d1eac63c5067cf0e88">More...</a><br /></td></tr>
<tr class="separator:gadc83d5b2b747a1d1eac63c5067cf0e88"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga708588a4f5ec6e1b8728268dd0d6ba73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga708588a4f5ec6e1b8728268dd0d6ba73">XUARTPS_MR_PARITY_NONE</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga708588a4f5ec6e1b8728268dd0d6ba73"><td class="mdescLeft">&#160;</td><td class="mdescRight">No parity mode.  <a href="group__uartps__v3__1.html#ga708588a4f5ec6e1b8728268dd0d6ba73">More...</a><br /></td></tr>
<tr class="separator:ga708588a4f5ec6e1b8728268dd0d6ba73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6485b62e7ab5675f8875b04f934cce5a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga6485b62e7ab5675f8875b04f934cce5a">XUARTPS_MR_PARITY_MARK</a>&#160;&#160;&#160;0x00000018U</td></tr>
<tr class="memdesc:ga6485b62e7ab5675f8875b04f934cce5a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mark parity mode.  <a href="group__uartps__v3__1.html#ga6485b62e7ab5675f8875b04f934cce5a">More...</a><br /></td></tr>
<tr class="separator:ga6485b62e7ab5675f8875b04f934cce5a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga332257f88a1089025cfa6c721b268e53"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga332257f88a1089025cfa6c721b268e53">XUARTPS_MR_PARITY_SPACE</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga332257f88a1089025cfa6c721b268e53"><td class="mdescLeft">&#160;</td><td class="mdescRight">Space parity mode.  <a href="group__uartps__v3__1.html#ga332257f88a1089025cfa6c721b268e53">More...</a><br /></td></tr>
<tr class="separator:ga332257f88a1089025cfa6c721b268e53"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad1dbc37545c9dd9b402ebde975ce568f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gad1dbc37545c9dd9b402ebde975ce568f">XUARTPS_MR_PARITY_ODD</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gad1dbc37545c9dd9b402ebde975ce568f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Odd parity mode.  <a href="group__uartps__v3__1.html#gad1dbc37545c9dd9b402ebde975ce568f">More...</a><br /></td></tr>
<tr class="separator:gad1dbc37545c9dd9b402ebde975ce568f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7321956b668fe79c2d2c399a203b7af3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga7321956b668fe79c2d2c399a203b7af3">XUARTPS_MR_PARITY_EVEN</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga7321956b668fe79c2d2c399a203b7af3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Even parity mode.  <a href="group__uartps__v3__1.html#ga7321956b668fe79c2d2c399a203b7af3">More...</a><br /></td></tr>
<tr class="separator:ga7321956b668fe79c2d2c399a203b7af3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga81a8d9730a5ec55902869c011d07433e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga81a8d9730a5ec55902869c011d07433e">XUARTPS_MR_PARITY_SHIFT</a>&#160;&#160;&#160;3U</td></tr>
<tr class="memdesc:ga81a8d9730a5ec55902869c011d07433e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Parity setting shift.  <a href="group__uartps__v3__1.html#ga81a8d9730a5ec55902869c011d07433e">More...</a><br /></td></tr>
<tr class="separator:ga81a8d9730a5ec55902869c011d07433e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga062f61f5b1d33404b4328d15a4010f5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga062f61f5b1d33404b4328d15a4010f5c">XUARTPS_MR_PARITY_MASK</a>&#160;&#160;&#160;0x00000038U</td></tr>
<tr class="memdesc:ga062f61f5b1d33404b4328d15a4010f5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Parity mask.  <a href="group__uartps__v3__1.html#ga062f61f5b1d33404b4328d15a4010f5c">More...</a><br /></td></tr>
<tr class="separator:ga062f61f5b1d33404b4328d15a4010f5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga168dc3bf9cf1fe0d46a1bef522621d90"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga168dc3bf9cf1fe0d46a1bef522621d90">XUARTPS_MR_CHARLEN_6_BIT</a>&#160;&#160;&#160;0x00000006U</td></tr>
<tr class="memdesc:ga168dc3bf9cf1fe0d46a1bef522621d90"><td class="mdescLeft">&#160;</td><td class="mdescRight">6 bits data  <a href="group__uartps__v3__1.html#ga168dc3bf9cf1fe0d46a1bef522621d90">More...</a><br /></td></tr>
<tr class="separator:ga168dc3bf9cf1fe0d46a1bef522621d90"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a506892b297daffb60aafead45870f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga5a506892b297daffb60aafead45870f5">XUARTPS_MR_CHARLEN_7_BIT</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga5a506892b297daffb60aafead45870f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">7 bits data  <a href="group__uartps__v3__1.html#ga5a506892b297daffb60aafead45870f5">More...</a><br /></td></tr>
<tr class="separator:ga5a506892b297daffb60aafead45870f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga038e90de6132f4e00b64b0f34ff0dfa7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga038e90de6132f4e00b64b0f34ff0dfa7">XUARTPS_MR_CHARLEN_8_BIT</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga038e90de6132f4e00b64b0f34ff0dfa7"><td class="mdescLeft">&#160;</td><td class="mdescRight">8 bits data  <a href="group__uartps__v3__1.html#ga038e90de6132f4e00b64b0f34ff0dfa7">More...</a><br /></td></tr>
<tr class="separator:ga038e90de6132f4e00b64b0f34ff0dfa7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga486e6d26bf3570c2f14cdbae2c246648"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga486e6d26bf3570c2f14cdbae2c246648">XUARTPS_MR_CHARLEN_SHIFT</a>&#160;&#160;&#160;1U</td></tr>
<tr class="memdesc:ga486e6d26bf3570c2f14cdbae2c246648"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Length shift.  <a href="group__uartps__v3__1.html#ga486e6d26bf3570c2f14cdbae2c246648">More...</a><br /></td></tr>
<tr class="separator:ga486e6d26bf3570c2f14cdbae2c246648"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae973a7d15eb3f582200a39f3a0444a66"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gae973a7d15eb3f582200a39f3a0444a66">XUARTPS_MR_CHARLEN_MASK</a>&#160;&#160;&#160;0x00000006U</td></tr>
<tr class="memdesc:gae973a7d15eb3f582200a39f3a0444a66"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data length mask.  <a href="group__uartps__v3__1.html#gae973a7d15eb3f582200a39f3a0444a66">More...</a><br /></td></tr>
<tr class="separator:gae973a7d15eb3f582200a39f3a0444a66"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac383c8056146a93a6113ce9a05501ffd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gac383c8056146a93a6113ce9a05501ffd">XUARTPS_MR_CLKSEL</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gac383c8056146a93a6113ce9a05501ffd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input clock selection.  <a href="group__uartps__v3__1.html#gac383c8056146a93a6113ce9a05501ffd">More...</a><br /></td></tr>
<tr class="separator:gac383c8056146a93a6113ce9a05501ffd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Interrupt control logic uses the interrupt enable register (IER) and the interrupt disable register (IDR) to set the value of the bits in the interrupt mask register (IMR).</p>
<p>The IMR determines whether to pass an interrupt to the interrupt status register (ISR). Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an interrupt. IMR and ISR are read only, and IER and IDR are write only. Reading either IER or IDR returns 0x00.</p>
<p>All four registers have the same bit definitions. </p>
</div></td></tr>
<tr class="memitem:gab5df3d1fd00008bd7cc177abd02f07e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gab5df3d1fd00008bd7cc177abd02f07e5">XUARTPS_IXR_RBRK</a>&#160;&#160;&#160;0x00002000U</td></tr>
<tr class="memdesc:gab5df3d1fd00008bd7cc177abd02f07e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx FIFO break detect interrupt.  <a href="group__uartps__v3__1.html#gab5df3d1fd00008bd7cc177abd02f07e5">More...</a><br /></td></tr>
<tr class="separator:gab5df3d1fd00008bd7cc177abd02f07e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace9c111cfb0362f6bb74d5893d3eccaf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gace9c111cfb0362f6bb74d5893d3eccaf">XUARTPS_IXR_TOVR</a>&#160;&#160;&#160;0x00001000U</td></tr>
<tr class="memdesc:gace9c111cfb0362f6bb74d5893d3eccaf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx FIFO Overflow interrupt.  <a href="group__uartps__v3__1.html#gace9c111cfb0362f6bb74d5893d3eccaf">More...</a><br /></td></tr>
<tr class="separator:gace9c111cfb0362f6bb74d5893d3eccaf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaffe1c724e8882759a6c4fdba948d6a2d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gaffe1c724e8882759a6c4fdba948d6a2d">XUARTPS_IXR_TNFUL</a>&#160;&#160;&#160;0x00000800U</td></tr>
<tr class="memdesc:gaffe1c724e8882759a6c4fdba948d6a2d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx FIFO Nearly Full interrupt.  <a href="group__uartps__v3__1.html#gaffe1c724e8882759a6c4fdba948d6a2d">More...</a><br /></td></tr>
<tr class="separator:gaffe1c724e8882759a6c4fdba948d6a2d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0432c93dc768cb173d84cc67dd6bbedc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga0432c93dc768cb173d84cc67dd6bbedc">XUARTPS_IXR_TTRIG</a>&#160;&#160;&#160;0x00000400U</td></tr>
<tr class="memdesc:ga0432c93dc768cb173d84cc67dd6bbedc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx Trig interrupt.  <a href="group__uartps__v3__1.html#ga0432c93dc768cb173d84cc67dd6bbedc">More...</a><br /></td></tr>
<tr class="separator:ga0432c93dc768cb173d84cc67dd6bbedc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadf1dabb7547f5b16748e8c6307cfc7a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gadf1dabb7547f5b16748e8c6307cfc7a1">XUARTPS_IXR_DMS</a>&#160;&#160;&#160;0x00000200U</td></tr>
<tr class="memdesc:gadf1dabb7547f5b16748e8c6307cfc7a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Modem status change interrupt.  <a href="group__uartps__v3__1.html#gadf1dabb7547f5b16748e8c6307cfc7a1">More...</a><br /></td></tr>
<tr class="separator:gadf1dabb7547f5b16748e8c6307cfc7a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7194f5e99a1a98178f6bf1462791aaac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga7194f5e99a1a98178f6bf1462791aaac">XUARTPS_IXR_TOUT</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:ga7194f5e99a1a98178f6bf1462791aaac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timeout error interrupt.  <a href="group__uartps__v3__1.html#ga7194f5e99a1a98178f6bf1462791aaac">More...</a><br /></td></tr>
<tr class="separator:ga7194f5e99a1a98178f6bf1462791aaac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2a11620ed0dd465adf0de24f6d7ad418"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga2a11620ed0dd465adf0de24f6d7ad418">XUARTPS_IXR_PARITY</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga2a11620ed0dd465adf0de24f6d7ad418"><td class="mdescLeft">&#160;</td><td class="mdescRight">Parity error interrupt.  <a href="group__uartps__v3__1.html#ga2a11620ed0dd465adf0de24f6d7ad418">More...</a><br /></td></tr>
<tr class="separator:ga2a11620ed0dd465adf0de24f6d7ad418"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa6048212fde48f7188efd90c83c4822d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gaa6048212fde48f7188efd90c83c4822d">XUARTPS_IXR_FRAMING</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:gaa6048212fde48f7188efd90c83c4822d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Framing error interrupt.  <a href="group__uartps__v3__1.html#gaa6048212fde48f7188efd90c83c4822d">More...</a><br /></td></tr>
<tr class="separator:gaa6048212fde48f7188efd90c83c4822d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafd4a37077bddeeefcc39d58b4f08fb23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gafd4a37077bddeeefcc39d58b4f08fb23">XUARTPS_IXR_OVER</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:gafd4a37077bddeeefcc39d58b4f08fb23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Overrun error interrupt.  <a href="group__uartps__v3__1.html#gafd4a37077bddeeefcc39d58b4f08fb23">More...</a><br /></td></tr>
<tr class="separator:gafd4a37077bddeeefcc39d58b4f08fb23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9abc091be0a0e2cc18bbc540db6e513b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga9abc091be0a0e2cc18bbc540db6e513b">XUARTPS_IXR_TXFULL</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga9abc091be0a0e2cc18bbc540db6e513b"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX FIFO full interrupt.  <a href="group__uartps__v3__1.html#ga9abc091be0a0e2cc18bbc540db6e513b">More...</a><br /></td></tr>
<tr class="separator:ga9abc091be0a0e2cc18bbc540db6e513b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9a4207349f3980046ba4ea9e4379007a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga9a4207349f3980046ba4ea9e4379007a">XUARTPS_IXR_TXEMPTY</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga9a4207349f3980046ba4ea9e4379007a"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX FIFO empty interrupt.  <a href="group__uartps__v3__1.html#ga9a4207349f3980046ba4ea9e4379007a">More...</a><br /></td></tr>
<tr class="separator:ga9a4207349f3980046ba4ea9e4379007a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae374cc3c085d3cac795d95b657b03d5e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gae374cc3c085d3cac795d95b657b03d5e">XUARTPS_IXR_RXFULL</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gae374cc3c085d3cac795d95b657b03d5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX FIFO full interrupt.  <a href="group__uartps__v3__1.html#gae374cc3c085d3cac795d95b657b03d5e">More...</a><br /></td></tr>
<tr class="separator:gae374cc3c085d3cac795d95b657b03d5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga541b132695e333571fd8c6b2eeaa23bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga541b132695e333571fd8c6b2eeaa23bd">XUARTPS_IXR_RXEMPTY</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga541b132695e333571fd8c6b2eeaa23bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX FIFO empty interrupt.  <a href="group__uartps__v3__1.html#ga541b132695e333571fd8c6b2eeaa23bd">More...</a><br /></td></tr>
<tr class="separator:ga541b132695e333571fd8c6b2eeaa23bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaad5de1c646049d7ced8841e316a34892"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gaad5de1c646049d7ced8841e316a34892">XUARTPS_IXR_RXOVR</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gaad5de1c646049d7ced8841e316a34892"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX FIFO trigger interrupt.  <a href="group__uartps__v3__1.html#gaad5de1c646049d7ced8841e316a34892">More...</a><br /></td></tr>
<tr class="separator:gaad5de1c646049d7ced8841e316a34892"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga73b78b2490f8a0aa402867987c765df0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga73b78b2490f8a0aa402867987c765df0">XUARTPS_IXR_MASK</a>&#160;&#160;&#160;0x00003FFFU</td></tr>
<tr class="memdesc:ga73b78b2490f8a0aa402867987c765df0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Valid bit mask.  <a href="group__uartps__v3__1.html#ga73b78b2490f8a0aa402867987c765df0">More...</a><br /></td></tr>
<tr class="separator:ga73b78b2490f8a0aa402867987c765df0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Baud Rate Generator Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The baud rate generator control register (BRGR) is a 16 bit register that controls the receiver bit sample clock and baud rate.</p>
<p>Valid values are 1 - 65535.</p>
<p>Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit in the MR register. </p>
</div></td></tr>
<tr class="memitem:ga19279c6968bf5936d9af320ff2c3c404"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga19279c6968bf5936d9af320ff2c3c404">XUARTPS_BAUDGEN_DISABLE</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga19279c6968bf5936d9af320ff2c3c404"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable clock.  <a href="group__uartps__v3__1.html#ga19279c6968bf5936d9af320ff2c3c404">More...</a><br /></td></tr>
<tr class="separator:ga19279c6968bf5936d9af320ff2c3c404"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3140f225a4fafc91ca8f5cdafb35d84a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga3140f225a4fafc91ca8f5cdafb35d84a">XUARTPS_BAUDGEN_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga3140f225a4fafc91ca8f5cdafb35d84a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Valid bits mask.  <a href="group__uartps__v3__1.html#ga3140f225a4fafc91ca8f5cdafb35d84a">More...</a><br /></td></tr>
<tr class="separator:ga3140f225a4fafc91ca8f5cdafb35d84a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0df74dbc1f99f853eac534c58465c67c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga0df74dbc1f99f853eac534c58465c67c">XUARTPS_BAUDGEN_RESET_VAL</a>&#160;&#160;&#160;0x0000028BU</td></tr>
<tr class="memdesc:ga0df74dbc1f99f853eac534c58465c67c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset value.  <a href="group__uartps__v3__1.html#ga0df74dbc1f99f853eac534c58465c67c">More...</a><br /></td></tr>
<tr class="separator:ga0df74dbc1f99f853eac534c58465c67c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Baud Divisor Rate register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The baud rate divider register (BDIV) controls how much the bit sample rate is divided by.</p>
<p>It sets the baud rate. Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.</p>
<p>Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by the MR_CCLK bit in the MR register. </p>
</div></td></tr>
<tr class="memitem:ga0994c9a85c14e41d593f7ced18d73325"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga0994c9a85c14e41d593f7ced18d73325">XUARTPS_BAUDDIV_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga0994c9a85c14e41d593f7ced18d73325"><td class="mdescLeft">&#160;</td><td class="mdescRight">8 bit baud divider mask  <a href="group__uartps__v3__1.html#ga0994c9a85c14e41d593f7ced18d73325">More...</a><br /></td></tr>
<tr class="separator:ga0994c9a85c14e41d593f7ced18d73325"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaae81b813494b51dffc97f265ccc8bc1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gaae81b813494b51dffc97f265ccc8bc1b">XUARTPS_BAUDDIV_RESET_VAL</a>&#160;&#160;&#160;0x0000000FU</td></tr>
<tr class="memdesc:gaae81b813494b51dffc97f265ccc8bc1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset value.  <a href="group__uartps__v3__1.html#gaae81b813494b51dffc97f265ccc8bc1b">More...</a><br /></td></tr>
<tr class="separator:gaae81b813494b51dffc97f265ccc8bc1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Receiver Timeout Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Use the receiver timeout register (RTR) to detect an idle condition on the receiver data line. </p>
</div></td></tr>
<tr class="memitem:ga9940f0728fcd584c7805eed12531539e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga9940f0728fcd584c7805eed12531539e">XUARTPS_RXTOUT_DISABLE</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga9940f0728fcd584c7805eed12531539e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable time out.  <a href="group__uartps__v3__1.html#ga9940f0728fcd584c7805eed12531539e">More...</a><br /></td></tr>
<tr class="separator:ga9940f0728fcd584c7805eed12531539e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga391ed6bbae78f486a638f48f539f7755"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga391ed6bbae78f486a638f48f539f7755">XUARTPS_RXTOUT_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga391ed6bbae78f486a638f48f539f7755"><td class="mdescLeft">&#160;</td><td class="mdescRight">Valid bits mask.  <a href="group__uartps__v3__1.html#ga391ed6bbae78f486a638f48f539f7755">More...</a><br /></td></tr>
<tr class="separator:ga391ed6bbae78f486a638f48f539f7755"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Receiver FIFO Trigger Level Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at which the RX FIFO triggers an interrupt event. </p>
</div></td></tr>
<tr class="memitem:ga31cf74ecfe8e69ba47c040de1a756417"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga31cf74ecfe8e69ba47c040de1a756417">XUARTPS_RXWM_DISABLE</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga31cf74ecfe8e69ba47c040de1a756417"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable RX trigger interrupt.  <a href="group__uartps__v3__1.html#ga31cf74ecfe8e69ba47c040de1a756417">More...</a><br /></td></tr>
<tr class="separator:ga31cf74ecfe8e69ba47c040de1a756417"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0b1b76b99179a02db9e22d6c290765fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga0b1b76b99179a02db9e22d6c290765fd">XUARTPS_RXWM_MASK</a>&#160;&#160;&#160;0x0000003FU</td></tr>
<tr class="memdesc:ga0b1b76b99179a02db9e22d6c290765fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Valid bits mask.  <a href="group__uartps__v3__1.html#ga0b1b76b99179a02db9e22d6c290765fd">More...</a><br /></td></tr>
<tr class="separator:ga0b1b76b99179a02db9e22d6c290765fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabf1d0d57b5ac837fc55dd128383dcafa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gabf1d0d57b5ac837fc55dd128383dcafa">XUARTPS_RXWM_RESET_VAL</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:gabf1d0d57b5ac837fc55dd128383dcafa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset value.  <a href="group__uartps__v3__1.html#gabf1d0d57b5ac837fc55dd128383dcafa">More...</a><br /></td></tr>
<tr class="separator:gabf1d0d57b5ac837fc55dd128383dcafa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Transmit FIFO Trigger Level Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at which the TX FIFO triggers an interrupt event. </p>
</div></td></tr>
<tr class="memitem:ga349330dc3cda8326ec19ca411eb08545"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga349330dc3cda8326ec19ca411eb08545">XUARTPS_TXWM_MASK</a>&#160;&#160;&#160;0x0000003FU</td></tr>
<tr class="memdesc:ga349330dc3cda8326ec19ca411eb08545"><td class="mdescLeft">&#160;</td><td class="mdescRight">Valid bits mask.  <a href="group__uartps__v3__1.html#ga349330dc3cda8326ec19ca411eb08545">More...</a><br /></td></tr>
<tr class="separator:ga349330dc3cda8326ec19ca411eb08545"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacd020d8ceafb59c1deffa8ad5b2f859e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gacd020d8ceafb59c1deffa8ad5b2f859e">XUARTPS_TXWM_RESET_VAL</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:gacd020d8ceafb59c1deffa8ad5b2f859e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset value.  <a href="group__uartps__v3__1.html#gacd020d8ceafb59c1deffa8ad5b2f859e">More...</a><br /></td></tr>
<tr class="separator:gacd020d8ceafb59c1deffa8ad5b2f859e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Modem Control Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register (MODEMCR) controls the interface with the modem or data set, or a peripheral device emulating a modem. </p>
</div></td></tr>
<tr class="memitem:ga664e6b91e03cbb02d76d61b830606746"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga664e6b91e03cbb02d76d61b830606746">XUARTPS_MODEMCR_FCM</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga664e6b91e03cbb02d76d61b830606746"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flow control mode.  <a href="group__uartps__v3__1.html#ga664e6b91e03cbb02d76d61b830606746">More...</a><br /></td></tr>
<tr class="separator:ga664e6b91e03cbb02d76d61b830606746"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae46d78a9b6d4f781341d046bc8647fb1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gae46d78a9b6d4f781341d046bc8647fb1">XUARTPS_MODEMCR_RTS</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gae46d78a9b6d4f781341d046bc8647fb1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Request to send.  <a href="group__uartps__v3__1.html#gae46d78a9b6d4f781341d046bc8647fb1">More...</a><br /></td></tr>
<tr class="separator:gae46d78a9b6d4f781341d046bc8647fb1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae32a046cc6b0c46a603b8c30a48312ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gae32a046cc6b0c46a603b8c30a48312ad">XUARTPS_MODEMCR_DTR</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gae32a046cc6b0c46a603b8c30a48312ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data terminal ready.  <a href="group__uartps__v3__1.html#gae32a046cc6b0c46a603b8c30a48312ad">More...</a><br /></td></tr>
<tr class="separator:gae32a046cc6b0c46a603b8c30a48312ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Modem Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register (MODEMSR) indicates the current state of the control lines from a modem, or another peripheral device, to the CPU.</p>
<p>In addition, four bits of the modem status register provide change information. These bits are set to a logic 1 whenever a control input from the modem changes state.</p>
<p>Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem status interrupt is generated and this is reflected in the modem status register. </p>
</div></td></tr>
<tr class="memitem:ga463d850e21bba14919f9b50dcd20e2a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga463d850e21bba14919f9b50dcd20e2a6">XUARTPS_MODEMSR_FCMS</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:ga463d850e21bba14919f9b50dcd20e2a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flow control mode (FCMS)  <a href="group__uartps__v3__1.html#ga463d850e21bba14919f9b50dcd20e2a6">More...</a><br /></td></tr>
<tr class="separator:ga463d850e21bba14919f9b50dcd20e2a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga95f1f46aa5d8066f272566450016c048"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga95f1f46aa5d8066f272566450016c048">XUARTPS_MODEMSR_DCD</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga95f1f46aa5d8066f272566450016c048"><td class="mdescLeft">&#160;</td><td class="mdescRight">Complement of DCD input.  <a href="group__uartps__v3__1.html#ga95f1f46aa5d8066f272566450016c048">More...</a><br /></td></tr>
<tr class="separator:ga95f1f46aa5d8066f272566450016c048"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga98d227162a5e307a8e0f1df5c3055e68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga98d227162a5e307a8e0f1df5c3055e68">XUARTPS_MODEMSR_RI</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga98d227162a5e307a8e0f1df5c3055e68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Complement of RI input.  <a href="group__uartps__v3__1.html#ga98d227162a5e307a8e0f1df5c3055e68">More...</a><br /></td></tr>
<tr class="separator:ga98d227162a5e307a8e0f1df5c3055e68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga628d3070bb4cbbef3614c0dee9cb52f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga628d3070bb4cbbef3614c0dee9cb52f4">XUARTPS_MODEMSR_DSR</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga628d3070bb4cbbef3614c0dee9cb52f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Complement of DSR input.  <a href="group__uartps__v3__1.html#ga628d3070bb4cbbef3614c0dee9cb52f4">More...</a><br /></td></tr>
<tr class="separator:ga628d3070bb4cbbef3614c0dee9cb52f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga89fcadc66f14e3e74211f140205acbfa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga89fcadc66f14e3e74211f140205acbfa">XUARTPS_MODEMSR_CTS</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga89fcadc66f14e3e74211f140205acbfa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Complement of CTS input.  <a href="group__uartps__v3__1.html#ga89fcadc66f14e3e74211f140205acbfa">More...</a><br /></td></tr>
<tr class="separator:ga89fcadc66f14e3e74211f140205acbfa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d0628da915d6e0ec3d9c3aa0f99a6e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga9d0628da915d6e0ec3d9c3aa0f99a6e8">XUARTPS_MODEMSR_DDCD</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga9d0628da915d6e0ec3d9c3aa0f99a6e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delta DCD indicator.  <a href="group__uartps__v3__1.html#ga9d0628da915d6e0ec3d9c3aa0f99a6e8">More...</a><br /></td></tr>
<tr class="separator:ga9d0628da915d6e0ec3d9c3aa0f99a6e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga436c976255badb632aca558faac74a5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga436c976255badb632aca558faac74a5c">XUARTPS_MODEMSR_TERI</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga436c976255badb632aca558faac74a5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Trailing Edge Ring Indicator.  <a href="group__uartps__v3__1.html#ga436c976255badb632aca558faac74a5c">More...</a><br /></td></tr>
<tr class="separator:ga436c976255badb632aca558faac74a5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga045cf2ea99ad7e3761cdd44ba234ce07"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga045cf2ea99ad7e3761cdd44ba234ce07">XUARTPS_MODEMSR_DDSR</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga045cf2ea99ad7e3761cdd44ba234ce07"><td class="mdescLeft">&#160;</td><td class="mdescRight">Change of DSR.  <a href="group__uartps__v3__1.html#ga045cf2ea99ad7e3761cdd44ba234ce07">More...</a><br /></td></tr>
<tr class="separator:ga045cf2ea99ad7e3761cdd44ba234ce07"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabefff2fb8865b052a2452c8dfa29beec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gabefff2fb8865b052a2452c8dfa29beec">XUARTPS_MODEMSR_DCTS</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gabefff2fb8865b052a2452c8dfa29beec"><td class="mdescLeft">&#160;</td><td class="mdescRight">Change of CTS.  <a href="group__uartps__v3__1.html#gabefff2fb8865b052a2452c8dfa29beec">More...</a><br /></td></tr>
<tr class="separator:gabefff2fb8865b052a2452c8dfa29beec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The channel status register (CSR) is provided to enable the control logic to monitor the status of bits in the channel interrupt status register, even if these are masked out by the interrupt mask register. </p>
</div></td></tr>
<tr class="memitem:gad4c950d463146caef09d4ef0dd168fc1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gad4c950d463146caef09d4ef0dd168fc1">XUARTPS_SR_TNFUL</a>&#160;&#160;&#160;0x00004000U</td></tr>
<tr class="memdesc:gad4c950d463146caef09d4ef0dd168fc1"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX FIFO Nearly Full Status.  <a href="group__uartps__v3__1.html#gad4c950d463146caef09d4ef0dd168fc1">More...</a><br /></td></tr>
<tr class="separator:gad4c950d463146caef09d4ef0dd168fc1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga111b277a26cb61628b2b5a1395e6e5de"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga111b277a26cb61628b2b5a1395e6e5de">XUARTPS_SR_TTRIG</a>&#160;&#160;&#160;0x00002000U</td></tr>
<tr class="memdesc:ga111b277a26cb61628b2b5a1395e6e5de"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX FIFO Trigger Status.  <a href="group__uartps__v3__1.html#ga111b277a26cb61628b2b5a1395e6e5de">More...</a><br /></td></tr>
<tr class="separator:ga111b277a26cb61628b2b5a1395e6e5de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac592e66801976640af2e3e08b7259d08"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gac592e66801976640af2e3e08b7259d08">XUARTPS_SR_FLOWDEL</a>&#160;&#160;&#160;0x00001000U</td></tr>
<tr class="memdesc:gac592e66801976640af2e3e08b7259d08"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX FIFO fill over flow delay.  <a href="group__uartps__v3__1.html#gac592e66801976640af2e3e08b7259d08">More...</a><br /></td></tr>
<tr class="separator:gac592e66801976640af2e3e08b7259d08"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5032d2efd70379e4c525816c0f75c724"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga5032d2efd70379e4c525816c0f75c724">XUARTPS_SR_TACTIVE</a>&#160;&#160;&#160;0x00000800U</td></tr>
<tr class="memdesc:ga5032d2efd70379e4c525816c0f75c724"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX active.  <a href="group__uartps__v3__1.html#ga5032d2efd70379e4c525816c0f75c724">More...</a><br /></td></tr>
<tr class="separator:ga5032d2efd70379e4c525816c0f75c724"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga85bccd08f2770a3f7795db3bfa5dac13"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga85bccd08f2770a3f7795db3bfa5dac13">XUARTPS_SR_RACTIVE</a>&#160;&#160;&#160;0x00000400U</td></tr>
<tr class="memdesc:ga85bccd08f2770a3f7795db3bfa5dac13"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX active.  <a href="group__uartps__v3__1.html#ga85bccd08f2770a3f7795db3bfa5dac13">More...</a><br /></td></tr>
<tr class="separator:ga85bccd08f2770a3f7795db3bfa5dac13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1fe57953aa624e5c7a1c8e20799dc012"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga1fe57953aa624e5c7a1c8e20799dc012">XUARTPS_SR_TXFULL</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga1fe57953aa624e5c7a1c8e20799dc012"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX FIFO full.  <a href="group__uartps__v3__1.html#ga1fe57953aa624e5c7a1c8e20799dc012">More...</a><br /></td></tr>
<tr class="separator:ga1fe57953aa624e5c7a1c8e20799dc012"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4eb9c1b9ceaf7aecb36d43c983edbe95"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga4eb9c1b9ceaf7aecb36d43c983edbe95">XUARTPS_SR_TXEMPTY</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga4eb9c1b9ceaf7aecb36d43c983edbe95"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX FIFO empty.  <a href="group__uartps__v3__1.html#ga4eb9c1b9ceaf7aecb36d43c983edbe95">More...</a><br /></td></tr>
<tr class="separator:ga4eb9c1b9ceaf7aecb36d43c983edbe95"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1871fba85971f549aff226215f9936a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga1871fba85971f549aff226215f9936a5">XUARTPS_SR_RXFULL</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga1871fba85971f549aff226215f9936a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX FIFO full.  <a href="group__uartps__v3__1.html#ga1871fba85971f549aff226215f9936a5">More...</a><br /></td></tr>
<tr class="separator:ga1871fba85971f549aff226215f9936a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad604ae6739b459eb76fd3515d3d4f249"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gad604ae6739b459eb76fd3515d3d4f249">XUARTPS_SR_RXEMPTY</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gad604ae6739b459eb76fd3515d3d4f249"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX FIFO empty.  <a href="group__uartps__v3__1.html#gad604ae6739b459eb76fd3515d3d4f249">More...</a><br /></td></tr>
<tr class="separator:gad604ae6739b459eb76fd3515d3d4f249"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga954d4d3a50798651fff9701809b20130"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga954d4d3a50798651fff9701809b20130">XUARTPS_SR_RXOVR</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga954d4d3a50798651fff9701809b20130"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX FIFO fill over trigger.  <a href="group__uartps__v3__1.html#ga954d4d3a50798651fff9701809b20130">More...</a><br /></td></tr>
<tr class="separator:ga954d4d3a50798651fff9701809b20130"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Flow Delay Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Operation of the flow delay register (FLOWDEL) is very similar to the receive FIFO trigger register.</p>
<p>An internal trigger signal activates when the FIFO is filled to the level set by this register. This trigger will not cause an interrupt, although it can be read through the channel status register. In hardware flow control mode, RTS is deactivated when the trigger becomes active. RTS only resets when the FIFO level is four less than the level of the flow delay trigger and the flow delay trigger is not activated. A value less than 4 disables the flow delay. </p>
</div></td></tr>
<tr class="memitem:ga6b7df91642929dda91d4098ed126134c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga6b7df91642929dda91d4098ed126134c">XUARTPS_FLOWDEL_MASK</a>&#160;&#160;&#160;<a class="el" href="group__uartps__v3__1.html#ga0b1b76b99179a02db9e22d6c290765fd">XUARTPS_RXWM_MASK</a></td></tr>
<tr class="memdesc:ga6b7df91642929dda91d4098ed126134c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Valid bit mask.  <a href="group__uartps__v3__1.html#ga6b7df91642929dda91d4098ed126134c">More...</a><br /></td></tr>
<tr class="separator:ga6b7df91642929dda91d4098ed126134c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Receiver FIFO Byte Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The Receiver FIFO Status register is used to have a continuous monitoring of the raw unmasked byte status information.</p>
<p>The register contains frame, parity and break status information for the top four bytes in the RX FIFO.</p>
<p>Receiver FIFO Byte Status Register Bit Definition </p>
</div></td></tr>
<tr class="memitem:gaf5abd2b8dd323af05918280deb04058e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gaf5abd2b8dd323af05918280deb04058e">XUARTPS_RXBS_BYTE3_BRKE</a>&#160;&#160;&#160;0x00000800U</td></tr>
<tr class="memdesc:gaf5abd2b8dd323af05918280deb04058e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte3 Break Error.  <a href="group__uartps__v3__1.html#gaf5abd2b8dd323af05918280deb04058e">More...</a><br /></td></tr>
<tr class="separator:gaf5abd2b8dd323af05918280deb04058e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac72a6c9ccc3df79e17a97a65eaf18d75"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gac72a6c9ccc3df79e17a97a65eaf18d75">XUARTPS_RXBS_BYTE3_FRME</a>&#160;&#160;&#160;0x00000400U</td></tr>
<tr class="memdesc:gac72a6c9ccc3df79e17a97a65eaf18d75"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte3 Frame Error.  <a href="group__uartps__v3__1.html#gac72a6c9ccc3df79e17a97a65eaf18d75">More...</a><br /></td></tr>
<tr class="separator:gac72a6c9ccc3df79e17a97a65eaf18d75"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac5a6ee8b0a568aa4add2089b7d762438"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gac5a6ee8b0a568aa4add2089b7d762438">XUARTPS_RXBS_BYTE3_PARE</a>&#160;&#160;&#160;0x00000200U</td></tr>
<tr class="memdesc:gac5a6ee8b0a568aa4add2089b7d762438"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte3 Parity Error.  <a href="group__uartps__v3__1.html#gac5a6ee8b0a568aa4add2089b7d762438">More...</a><br /></td></tr>
<tr class="separator:gac5a6ee8b0a568aa4add2089b7d762438"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad84d5ed923253797a6afa6c64b4a3dd0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gad84d5ed923253797a6afa6c64b4a3dd0">XUARTPS_RXBS_BYTE2_BRKE</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:gad84d5ed923253797a6afa6c64b4a3dd0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte2 Break Error.  <a href="group__uartps__v3__1.html#gad84d5ed923253797a6afa6c64b4a3dd0">More...</a><br /></td></tr>
<tr class="separator:gad84d5ed923253797a6afa6c64b4a3dd0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae0c10001ad4dd9794de2de3387dd2c99"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gae0c10001ad4dd9794de2de3387dd2c99">XUARTPS_RXBS_BYTE2_FRME</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:gae0c10001ad4dd9794de2de3387dd2c99"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte2 Frame Error.  <a href="group__uartps__v3__1.html#gae0c10001ad4dd9794de2de3387dd2c99">More...</a><br /></td></tr>
<tr class="separator:gae0c10001ad4dd9794de2de3387dd2c99"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeda8e4c0a58e4a655e874948cb7e2db4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gaeda8e4c0a58e4a655e874948cb7e2db4">XUARTPS_RXBS_BYTE2_PARE</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:gaeda8e4c0a58e4a655e874948cb7e2db4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte2 Parity Error.  <a href="group__uartps__v3__1.html#gaeda8e4c0a58e4a655e874948cb7e2db4">More...</a><br /></td></tr>
<tr class="separator:gaeda8e4c0a58e4a655e874948cb7e2db4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga84dea42f85ba727bf8efc90ca98e8b1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga84dea42f85ba727bf8efc90ca98e8b1f">XUARTPS_RXBS_BYTE1_BRKE</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga84dea42f85ba727bf8efc90ca98e8b1f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte1 Break Error.  <a href="group__uartps__v3__1.html#ga84dea42f85ba727bf8efc90ca98e8b1f">More...</a><br /></td></tr>
<tr class="separator:ga84dea42f85ba727bf8efc90ca98e8b1f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabfe6a00c27c48bfee66181c83214e8be"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gabfe6a00c27c48bfee66181c83214e8be">XUARTPS_RXBS_BYTE1_FRME</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gabfe6a00c27c48bfee66181c83214e8be"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte1 Frame Error.  <a href="group__uartps__v3__1.html#gabfe6a00c27c48bfee66181c83214e8be">More...</a><br /></td></tr>
<tr class="separator:gabfe6a00c27c48bfee66181c83214e8be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga44cae6b2e96f17f7556f569f03017e45"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga44cae6b2e96f17f7556f569f03017e45">XUARTPS_RXBS_BYTE1_PARE</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga44cae6b2e96f17f7556f569f03017e45"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte1 Parity Error.  <a href="group__uartps__v3__1.html#ga44cae6b2e96f17f7556f569f03017e45">More...</a><br /></td></tr>
<tr class="separator:ga44cae6b2e96f17f7556f569f03017e45"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8d1b291588997d03d0fe4a107db31d5f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga8d1b291588997d03d0fe4a107db31d5f">XUARTPS_RXBS_BYTE0_BRKE</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga8d1b291588997d03d0fe4a107db31d5f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte0 Break Error.  <a href="group__uartps__v3__1.html#ga8d1b291588997d03d0fe4a107db31d5f">More...</a><br /></td></tr>
<tr class="separator:ga8d1b291588997d03d0fe4a107db31d5f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5f24c98437ec9ca72a3b9777c5e96a84"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga5f24c98437ec9ca72a3b9777c5e96a84">XUARTPS_RXBS_BYTE0_FRME</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga5f24c98437ec9ca72a3b9777c5e96a84"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte0 Frame Error.  <a href="group__uartps__v3__1.html#ga5f24c98437ec9ca72a3b9777c5e96a84">More...</a><br /></td></tr>
<tr class="separator:ga5f24c98437ec9ca72a3b9777c5e96a84"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeb95a2a53d101d8256ffbe8165233307"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gaeb95a2a53d101d8256ffbe8165233307">XUARTPS_RXBS_BYTE0_PARE</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gaeb95a2a53d101d8256ffbe8165233307"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte0 Parity Error.  <a href="group__uartps__v3__1.html#gaeb95a2a53d101d8256ffbe8165233307">More...</a><br /></td></tr>
<tr class="separator:gaeb95a2a53d101d8256ffbe8165233307"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad270e6c5e81ad53fe663527ce2292e7c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#gad270e6c5e81ad53fe663527ce2292e7c">XUARTPS_RXBS_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:gad270e6c5e81ad53fe663527ce2292e7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">3 bit RX byte status mask  <a href="group__uartps__v3__1.html#gad270e6c5e81ad53fe663527ce2292e7c">More...</a><br /></td></tr>
<tr class="separator:gad270e6c5e81ad53fe663527ce2292e7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga4bae0ee4df836a8c3e7748c9ae28ebee"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga4bae0ee4df836a8c3e7748c9ae28ebee">XUartPs_SendByte</a> (u32 BaseAddress, u8 Data)</td></tr>
<tr class="memdesc:ga4bae0ee4df836a8c3e7748c9ae28ebee"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sends one byte using the device.  <a href="group__uartps__v3__1.html#ga4bae0ee4df836a8c3e7748c9ae28ebee">More...</a><br /></td></tr>
<tr class="separator:ga4bae0ee4df836a8c3e7748c9ae28ebee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60240486c69f6167ab13194ced5e8bb7"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga60240486c69f6167ab13194ced5e8bb7">XUartPs_RecvByte</a> (u32 BaseAddress)</td></tr>
<tr class="memdesc:ga60240486c69f6167ab13194ced5e8bb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function receives a byte from the device.  <a href="group__uartps__v3__1.html#ga60240486c69f6167ab13194ced5e8bb7">More...</a><br /></td></tr>
<tr class="separator:ga60240486c69f6167ab13194ced5e8bb7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga157cf5966738452bc13639746f4b8d97"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartps__v3__1.html#ga157cf5966738452bc13639746f4b8d97">XUartPs_ResetHw</a> (u32 BaseAddress)</td></tr>
<tr class="memdesc:ga157cf5966738452bc13639746f4b8d97"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function resets UART.  <a href="group__uartps__v3__1.html#ga157cf5966738452bc13639746f4b8d97">More...</a><br /></td></tr>
<tr class="separator:ga157cf5966738452bc13639746f4b8d97"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
</div><!-- contents -->
</div><!-- doc-content -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
  <ul>
    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
  </ul>
</div>
</body>
</html>
